Digital Design Engineer (RTL)

Explore Your Career Possibilities

At Talent101, your talent can make a difference. We connect skilled engineering and technology professionals with challenging opportunities where their expertise has a direct impact.

As part of a Talent101 managed services team, you’ll work alongside talented professionals, solve real-world engineering challenges, and support innovative projects for some of the world’s leading technology companies.

We look for people who are passionate about what they do, bring their best every day, and want the opportunity to grow while making a meaningful contribution.

Bring your expertise. Make an impact. Build what’s next with Talent101.

We are expanding our Managed Services team and seeking a Digital Design Engineer (RTL) with experience in Intellectual Property (IP) development and Verilog-based RTL design. This is an onsite position in Dallas, Texas.

Responsibilities may include, but are not limited to:

· Architect and implement synthesizable RTL in Verilog for high-speed I/O subsystems and high speed Ethernet MAC/PHY blocks.

· Develop custom IP blocks and modify existing Synopsys DesignWare IPs to meet performance, area, and power targets.

· Ensure RTL adheres to design specifications, protocol standards (e.g., IEEE 802.3), and integration requirements.

· Integrate third-party IPs (e.g., Synopsys USB, PCIe, Ethernet) into SoC environments, customizing interfaces and configuration parameters.

· Collaborate with system architects to align IP functionality with broader system-level goals.

· Resolve compatibility issues across clock domains, reset strategies, and bus protocols (e.g., AXI, AHB).

· Translate high-level architectural requirements into detailed microarchitecture specs.

· VFS in for converter IC’s DC-DC Op-Amp. Buck, Boost etc.

· Define Datapath, control logic, and FSMs for high-throughput, low-latency designs.

· Document design intent, interface definitions, and configuration registers.

· Work closely with verification teams to define test plans, support UVM testbench development, and debug RTL issues.

· Collaborate with physical design teams to support synthesis, floor planning, and timing closure.

· Participate in timing analysis, linting, and formal checks to ensure design robustness.

· Analyze and optimize RTL for timing, area, and power using Synopsys tools (Design Compiler, PrimeTime).

· Implement pipelining, clock gating, and resource sharing techniques to meet stringent performance goals.

· Support post-silicon validation and correlate lab measurements with pre-silicon simulations.

· Maintain version-controlled RTL repositories and follow structured design handoff procedures.

· Use scripting (Python, Tcl, Perl) to automate design tasks, IP configuration, and build flows.

· Contribute to continuous improvement of design methodologies and internal IP libraries.

· Interface with firmware, AMS, and system integration teams to ensure seamless end-to-end functionality.

· Participate in design reviews, spec discussions, and bring-up planning for tape-out and silicon validation.

· Provide technical guidance and mentorship to junior engineers on RTL best practices and IP reuse strategies.

Qualifications – Minimum Requirements:

• 7+ years Digital Design experience of complex high speed IO sockets
• Solid foundation in digital logic design, computer architecture, and communication systems.
• Proficiency in Verilog (and optionally SystemVerilog) for synthesizable RTL design.
• Experience in custom IP development and modification of Synopsys DesignWare IPs, including configuration, integration, and optimization.
• Familiarity with IP-XACT, IP packaging standards, and SoC integration flows
• Strong understanding of high-speed interface protocols such as PCIe, USB, DDR, and Ethernet (e.g., IEEE 802.3, 10G/25G/100G).
• Experience with clock domain crossing, latency optimization, and data path design for high-throughput applications.
• Knowledge of MAC/PHY architecture, flow control, and packet processing pipelines. Clock Domain Crossing and high speed IO experience
• Exposure to automotive or safety-critical design flows (e.g., ISO 26262) or networking standards (e.g., TSN, AVB).
• Hands-on experience with synthesis tools (Synopsys Design Compiler), timing analysis (PrimeTime), and lint/formal tools (SpyGlass, Conformal).
• Familiarity with simulation environments and collaboration with verification teams using UVM-based testbenches.
• Understanding of DFT, low-power design techniques, and area/power trade-offs.
• Effective communication skills for cross-functional collaboration with verification, physical design, firmware, and system teams.
• Ability to document design specifications, interface definitions, and configuration guides clearly and concisely.
• Experience participating in design reviews, architecture discussions, and tape-out planning.

Equal Opportunity Employer

Talent101 is an Equal Opportunity Employer. We are committed to providing equal employment opportunities to all qualified applicants and employees without regard to race, color, religion, sex, national origin, age, disability, genetic information, veteran status, or any other characteristic protected by applicable federal, state, or local law.

Talent 101 is a global services provider for the semiconductor industry only. We provide a total workforce or project turnkey solution anywhere you need it: onshore, nearshore, or offshore.