Senior OPC R&D Engineer

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.

As a lead OPC (Optical Proximity Correction) R&D Engineer, you will develop and implement, and guide other engineers in developing, high-quality technology solutions to optimize pattern fidelity, process window and reliability for critical memory patterning layers, using industry-standard software to model and correct for optical and other patterning effects, as well as employing DFM and RET solutions, ensuring that the final chip layout is accurately transferred to the wafer while meeting manufacturing requirements.

Key Responsibilities:

• OPC Solution Development: Drive development, implementation, and optimization of OPC models and recipes,including implementing appropriate advanced DFM and RET techniques, for critical memory layers. Lead patterning development with SMO studies, test plate design, and design rule evaluations.
• Tapeout Support: Validate OPC solution tapeout readiness and conduct quality reviews in conjunction with litho and process integration teams. Lead the patterning team to quickly resolve hotspot issues with effective data-driven solutions.
• OPC Performance Evaluation and Optimization: Work with development fab engineers to ensure the quality and performance of OPC solutions. Using validation and simulation software tools, guide effective wafer data collection for OPC verification to optimize mask quality, pattern fidelity and process window.
• Documentation and Training: Own creating documentation and training to help internal teams to understand and use the OPC tools and methodologies.
• Troubleshooting and Support: Provide technical support and guidance to internal teams who are using the OPC tools, helping them resolve issues and optimize their designs or processes.
• Collaboration and Communication: Collaborate closely with design rule, lithography, process integration, tapeout and mask engineering teams, to ensure that the OPC process is aligned with the overall chip manufacturing process.

• MS, or PhD in a related science or engineering discipline (e.g. Physics, Materials Science, Electrical or Chemical Engineering)
• Minimum of 5 years of proven TD experience in semiconductor patterning technical areas
• Strong understanding of patterning technologies and concerns: knowledge of optical proximity effects, resolution enhancement techniques (RET) including SMO (source mask optimization), and DFM methodologies are essential.
• Proficiency in OPC and SMO software with industry-standard OPC tools (Mentor, Synopsys, ASML Brion)
• Programming skills: proficiency in scripting languages like Python, TCL, or Perl, and sometimes with C++.
• Data analysis skills: ability to analyze large datasets, perform statistical analysis, and interpret simulation results.
• Problem-solving and analytical skills: ability to identify and solve complex technical problems related to RET/OPC, Tapeout, design rules and semiconductor patterning processes.
• Communication and teamwork skills: ability to effectively communicate technical information and collaborate effectively across design, TD, and manufacturing teams.

Preferred:

• 7+ years experience in OPC/RET or related areas delivering high quality patterning solutions
• Strong understanding of semiconductor manufacturing technologies and the overall chip fabrication process, especially for NAND flash manufacturing.

Working Conditions: This position is primarily office-based. Some international travel is expected.

This position is also eligible to participate in Solidigm's restricted stock unit (RSU), restricted cash unit (RCU), and cash bonus programs. In addition, Solidigm offers a benefits package that includes medical, dental, vision, supplemental life and AD&D insurance; short- and long-term disability; healthcare and dependent care flexible spending accounts, and a company match on eligible 401(k) plan contributions.

The compensation range for this role is $159,360 - $255,000. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

This is a Hybrid role that can be aligned to either San Jose California or Rancho Cordova California. This role is open to relocation.

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